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MC33399 rev 5.0, 02/2005 freescale semiconductor technical data this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2005. all rights reserved. local interconnect network (lin) physical interface local interconnect network (lin) is a serial communication protocol designed to su pport automotive networks in conjunction with controller area network (can). as the lowest level of a hierarchical network, lin enables cost-effective communication with sensors and actuators when all the featur es of can are not required. the 33399 is a physical layer component dedicated to automotive sub-bus applications. it offers sp eed communication from 1.0 kbps to 20 kbps, and up to 60 kbps for programming mode. it has two operating modes: normal and sleep. the 33399 supports lin prot ocol specification 1.3. features ? nominal operation from v sup 7.0 v to 18 v dc, functional up to 27 v dc battery voltage and capable of handling 40 v during load dump ? active bus waveshaping to minimize radiated emission ? 5.0 kv esd on lin bus terminal, 4.0 kv esd on other terminals ?30k ? internal pullup resistor ? ground shift operation and ground disconnection fail-safe at module level ? an unpowered node does not disturb the network ? 20 a standby current in sleep mode ? wake-up capability from lin bu s, mcu command and dedicated high voltage wake-up input (inter face to external switch) ? interface to mcu with cmos-compatible i/o terminals ? control of external voltage regulator figure 1. 33399 simplified application diagram lin physical interface 33399 ordering information device temperature range (t a ) package MC33399d/r2 -40c to 125c 8 soicn d suffix 98asb42564b 8-terminal soicn lin bus 5.0 v regulator 33399 mcu v pwr inh en txd rxd vsup wake gnd lin 12 v
analog integrated circuit device data 2 freescale semiconductor 33399 internal block diagram internal block diagram figure 2. 33399 simplifi ed internal block diagram v ref receiver inf en rxd txd gnd lin 30 k ? vsup driver wake wake-up v reg control bias protection logic
analog integrated circuit device data freescale semiconductor 3 33399 terminal connections terminal connections figure 3. 33399 8-soicn terminal connections table 1. 8-soicn terminal definitions a functional description of each terminal can be found in the functional terminal description section beginning on page 10 . terminal terminal name formal name definition 1 rxd data output mcu interface that reports the state of the lin bus voltage. 2 en enable control controls the operation mode of the interface. 3 wake wake input high voltage input used to wake up the device from the sleep mode. 4 txd data input mcu interface that controls the state of the lin output. 5 gnd ground device ground terminal. 6 lin lin bus bidirectional terminal that represents t he single-wire bus transmitter and receiver. 7 vsup power supply device power supply terminal. 8 inh inhibit output controls an external switchable volt age regulator having an inhibit input. 1 2 3 4 5 6 7 8 rxd en wake txd inh v sup lin gnd
analog integrated circuit device data 4 freescale semiconductor 33399 maximum ratings maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol value unit electrical ratings power supply voltage continuous supply voltage transient voltage (load dump) v sup 27 40 v wake dc and transient voltage (through a 33 k ? serial resistor) v wake -18 to 40 v logic voltage (rxd, txd, en terminals) v log -0.3 to 5.5 v lin terminal dc voltage transient (coupled through 1.0 nf capacitor) v bus -18 to 40 -150 to 100 v inh voltage/current dc voltage v inh -0.3 to v sup + 0.3 v esd voltage, human body model (1) all terminals lin bus terminal with respect to ground v esd1 4000 5000 v esd voltage, machine model (2) all terminals v esd2 200 v thermal ratings operating temperature ambient junction t a t j -40 to 125 -40 to 150 c storage temperature t stg -55 to 165 c thermal resistance , junction to ambient r ja 150 c/w peak package reflow temperature during solder mounting (3) t solder 240 c thermal shutdown t shut 150 to 200 c thermal shutdown hysteresis t hyst 8.0 to 20 c notes 1. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 2. esd2 testing is performed in ac cordance with the machine model (c zap = 220 pf, r zap =0 ? ). 3. terminal soldering temperature limit is for 10 seconds maximum duration. not desig ned for immersion soldering. exceeding thes e limits may cause malfunction or permanent damage to the device.
analog integrated circuit device data freescale semiconductor 5 33399 static electrical characteristics static electrical characteristics table 3. static electrical characteristics characteristics noted under conditions 7.0 v v sup 18 v, -40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit vsup terminal (device power supply) supply voltage range v sup 7.0 13.5 18 v supply current in sleep mode v lin > v sup -0.5 v, v sup < 14 v 14 v < v sup < 18 v i s1 i s2 ? ? 20 ? 50 150 a supply current in normal mode recessive state dominant state, total bus load > 500 ? i s(rec) i s(dom) ? ? ? ? 2.0 3.0 ma supply undervoltage threshold v sup_uv 5.5 6.4 6.8 v rxd output terminal (logic) low-level output voltage i in 1.5 ma v ol 0?0.9 v high-level output voltage i out 250 a v oh 3.75 ? 5.25 v txd input terminal (logic) low-level input voltage v il ??1.5v high-level input voltage v ih 3.5 ? ? v input voltage threshold hysteresis v inhyst 100 550 800 mv pullup current source 1.0 v < v txd < 4.0 v, v en = 5.0 v i pu -50 ? -25 a en input terminal (logic) low-level input voltage v il ??1.5v high-level input voltage v ih 3.5 ? ? v input voltage threshold hysteresis v inhyst 100 480 800 mv en low-level input current v in = 1.0 v i il 5.0 20 30 a high-level input current v in = 4.0 v i ih ?2040 a pulldown current 1.0 v < en < 4.0 v i pd ?20? a
analog integrated circuit device data 6 freescale semiconductor 33399 static electrical characteristics lin terminal (voltage expressed versus v sup voltage) low-level bus voltage (dominant state) txd low, v lin = 40 ma v dom 0?1.4 v high-level voltage (recessive state) txd high, i out = 1.0 a v rec 0.85 v sup ?? v internal pullup resistor to vsup (4) -40c t a 70c 70c < t a 125c r pu 20 35 30 49 47 60 k ? current limitation txd low, v lin = v sup i lim 50 150 200 ma leakage current to gnd recessive state, v sup - 0.3 v v lin v sup (4) v sup disconnected, -18 v v lin 18 v (excluding internal pullup source) v sup disconnected, v lin = -18 v (including internal pullup source) v sup disconnected, v lin = +18 v (including internal pullup source) i leak 0 -40 ? ? ? ? -600 15 10 40 ? ? a lin receiver, low-level input voltage txd high, rxd low v linl 0v sup ?0.4v sup v lin receiver, high-level input voltage txd high, rxd high v linh 0.6 v sup ?v sup v lin receiver threshold center (v linh - v linl )/2 v linth ?v sup /2 ? v lin receiver input voltage hysteresis v linh - v linl v linhys 0.05 v sup ?0.15v sup v lin wake-up threshold voltage v linwu 3.5 4.5 6.0 v inh output terminal high-level voltage (normal mode) v wuh v sup -0.8 ? v sup v leakage current (sleep mode) 0 < v inh < v sup i leak 0?5.0 a wake input terminal typical wake-up threshold (en = 0 v, 7.0 v v sup 18 v) (5) high-to-low transition low-to-high transition v wuth 0.3 v sup 0.4 v sup 0.43 v sup 0.55 v sup 0.55 v sup 0.65 v sup v wake-up threshold hysteresis v wuhys 0.1 v sup 0.16 v sup 0.2 v sup v wake input current v wake 14 v v wake > 14 v i wu ? ? 1.0 ? 5.0 100 a notes 4. a diode structure is inserted with the pullup resistor to avoid parasitic current path from lin to v sup . 5. when v sup is greater than 18 v, the wake-up voltage thresholds remain identical to the wake-up thresholds at 18 v. table 3. static electrical ch aracteristics (continued) characteristics noted under conditions 7.0 v v sup 18 v, -40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 7 33399 dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electrical characteristics characteristics noted under conditions 7.0 v v sup 18 v, -40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit digital interface timing lin slew rate (6) , (7) falling edge rising edge t fall t rise 0.75 0.75 2.0 2.0 3.0 3.0 v/ s lin rise/fall symmetry (t rise -t fall )t sym -2.0 ? 2.0 s driver propagation delay (8) , (9) txd low-to-lin low txd high-to-lin high t txdlinl t txdlinh 0 0 ? ? 4.0 4.0 s receiver propagation delay (9) , (10) lin low to rxd low lin high to rxd high t rxdlinl t rxdlinh 2.0 2.0 4.0 4.0 6.0 6.0 s receiver propagation delay symmetry t recsym -2.0 ? 2.0 s transmitter propagation delay symmetry t trsym -2.0 ? 2.0 s propagation delay (11) lin bus wake-up to inh high t prop wl 45 70 130 s notess 6. measured between 20 and 80 percent of bus signal for 10 v < v sup < 18 v. between 30 and 70 percent of signal for 7.0 v < v sup <10v. 7. see figure 5 , page 8 . 8. t txdlinl is measured from txd (high-to-low) and lin (v rec -0.2 v). t txdlinh is measured from txd (low-to-high) and lin (v dom + 0.2 v). 9. see figure 4 , page 8 . 10. measured between lin receiver thresholds and rxd terminal. 11. see figure 6 , page 8 .
analog integrated circuit device data 8 freescale semiconductor 33399 timing diagrams timing diagrams figure 4. normal mode bus timing characteristics figure 5. lin rise and fall time figure 6. lin bus wake-up txd rxd lin v rec dominant state t txdlinl t txdlinh recessive state recessive state 0.4 v sup 0.6 v sup t rxdlinh t rxdlinl v dom + 0.2 v v rec - 0.2 v v dom t fall t rise 0.2 v sup 0.8 v sup 0.8 v sup 0.2 v sup inh lin v sup dominant state recessive state 0.4 v sup t prop wl
analog integrated circuit device data freescale semiconductor 9 33399 functional diagrams functional diagrams figure 7. lin wake-up with inh option figure 8. lin wake-up from wake-up switch figure 9. lin wake-up with mcu in stop mode lin bus inh bus wake-up filtering time ( t prog wl) voltage off state on state node in sleep state node in regulator wake-up time delay low or floating high mcu startup time delay en en high operation regulator wake inh voltage off state on state node in sleep state node in regulator wake-up time delay high mcu startup time delay en en high operation state change regulator low or floating wake filtering time lin bus irq wake-up filtering time (t prog wl) voltage reg on state mcu in stop mode node in operation high low mcu stop mode recovery/startup time delay en state en high high wake-up from stop mode inh low or floating high (previous wake-up) i/o(2) high impedance / i/o in input state low
analog integrated circuit device data 10 freescale semiconductor 33399 functional terminal description functional description introduction the 33399 is a physical layer component dedicated to automotive lin sub-bus applications. the 33399 features include speed communication from 1.0 kbps to 20 kbps, up to 60 kbps for programming mode, and active bus waveshaping to minimize radiated emission. the device offers three different wake-up capabilities: wake-up from lin bus, wake-up from the mcu command, and dedicated high voltage wake-up input. the inh output may be used to control an external voltage regulator. functional terminal description power supply terminal (vsup) the v sup power supply terminal is connected to a battery through a serial diode for reverse battery protection. the dc operating voltage is from 7.0 v to 27 v. this terminal sustains standard automotive voltage conditions such as 27 v dc during jump-start conditions and 40 v during load dump. to avoid a false bus message, an undervoltage reset circuitry disables the transmission path (from txd to lin) when v sup falls below 7.0 v. supply current in the sleep mode is typically 20 a. ground terminal (gnd) in case of a ground disconnection at the module level, the 33399 does not have significant current consumption on the lin bus terminal when in the recessive state. (less than 100 a is sourced from lin bus terminal, which creates 100 mv drop voltage from the 1.0 k ? lin bus pullup resistor.) for the dominant state, the pul lup resistor should always be active. the 33399 handles a ground shift up to 3.0 v when v sup > 9.0 v. below 9.0 v v sup , a ground shift can reduce v sup value below the minimum v sup operation of 7.0 v. lin bus terminal the lin bus terminal represents the single-wire bus transmitter and receiver. transmitter characteristics the lin driver is a low-side mosfet with internal current limitation and thermal shutdown. an internal pullup resistor with a serial diode structure is integrated so no external pullup components are required for the application in a slave node. an additional pullup resistor of 1.0 k ? must be added when the device is used in the master node. voltage can go from -18 v to 40 v without current other than the pullup resistance. the lin terminal exhibits no reverse current from the lin bus line to v sup , even in the event of gnd shift or v pwr disconnection. lin thresholds are compatible with the lin protocol specification. the fall time from recessive to dominant and the rise time from dominant to recessive are controlled to typically 2.0 v/s. the symmetry between rise and fall time is also guaranteed. when going from dominant to recessive, the bus impedance parasitic capacitor must be charged up to v sup. this charge-up is achieved by the total system pullup current resistors. in order to guarantee that the rise time is within specification, maximum bus capacitance should not exceed 10 nf with bus total pullup resistance less than 1.0 k ? . receiver characteristics the receiver thresholds are ratiometric with the device supply terminal. typical threshold is 50%, with a hysteresis between 5% and 10% of v sup . data input terminal (txd) the txd input terminal is the mcu interface that controls the state of t he lin output. when txd is low, lin output is low; when txd is high , the lin output tran sistor is turned off. this terminal has an internal 5.0 v internal pullup current source to set the bus in a rece ssive state in case the mcu is not able to control it; for in stance, during system power-up/ power-down. during the sleep mode, the pullup current source is turned off. data output terminal (rxd) the rxd output terminal is t he mcu interface that reports the state of the lin bus volt age. lin high (recessive) is reported by a high level on rxd; lin low (dominant) is reported by a low voltage on rx d. rxd output structure is a cmos-type push-pul l output stage. enable input terminal (en) the en terminal controls the operation mode of the interface. if en = logic [1], the interface is in normal mode, with the transmission path from txd to lin and from lin to rxd both active. if en = logic [0], the device is in sleep mode or low power mode, and no transmission is possible. in sleep mode, the lin bus terminal is held at v sup through the bus pullup resistors and pullup current sources. the device can transmit only after being awakened. refer to the inhibit output terminal (inh) description on page 11 . during sleep mode, the device is still supplied from the battery voltage (through v sup terminal). supply current is 20 a typical. setting the en terminal to low will turn the inh to high impedance. the en terminal has an internal
analog integrated circuit device data freescale semiconductor 11 33399 functional terminal description 20 a pulldown current source to ensure the device is in sleep mode if en floats. inhibit output terminal (inh) the inh terminal controls an external switchable voltage regulator having an inhibit input. this terminal is a high-side switch structure to v sup . when the device is in the normal mode, the inhibit high-side switch is turned on and the external voltage regulator is acti vated. when the device is in sleep mode, the inhibit switch is turned off and disables the voltage regulator (if this feature is used). a wake-up event on the lin bus line will switch the inh terminal to v sup level. wake-up output current capability is limited to 280 a. inh can also drive an external mosfet connected to an mcu irq or xirq input to generate an interrupt. see the typical application illustrated in figure 13 , page 14 . wake input terminal (wake) the wake terminal is a high-voltage input used to wake up the device from sleep mode. wake is usually connected to an external switch in the application. the typical wake thresholds are v sup /2. the wake terminal has a spec ial design structure and allows wake-up from both hi gh-to-low or low-to-high transitions. when entering the sleep mode, the lin monitors the state of the wake terminal and stores it as a reference state. the opposite state of th is reference state will be the wake-up event used by the device to re-enter normal mode. an internal filter is implemented (50 s typical filtering time delay). the wake term inal input structur e exhibits a high impedance with extremely low input current when voltage at this terminal is below 14 v. when voltage at the wake terminal exceeds 14 v, input curr ent starts to sink into the device. a series resistor should be inserted in order to limit the input current, mainly during transient pulses. recommended resistor value is 33 k ? . important the wake terminal should not be left open. if the wake-up function is not used, wake should be connected to gnd to avoid false wake-up.
analog integrated circuit device data 12 freescale semiconductor 33399 functional device operation functional device operation operational and transitional modes as described below and depicted in figure 10 and table 5 on page 13 , the 33399 has two operational modes, normal and sleep, and one transitional mode, awake. normal mode this is the normal transmit ting and receiving mode. all features are available. sleep mode in this mode the transmission path is disabled and the device is in low power mode. supply current from v sup is 20 a typical. wake-up can occu r from lin bus activity, as well as from node internal wake-up through the en terminal and the wake input terminal. device power-up (awake transitional mode) at system power-up (v sup rises from zero), the 33399 automatically switches into the ?awake ? mode (refer to figure 10 below and table 5 on page 13 . it switches the inh terminal in high state to v sup level. the microcontroller of the application then confirms the normal mode by setting the en terminal high. device wake-up events the device can be awakened from sleep mode by three wake-up events: ? lin bus activity ? internal node wake-up (en terminal) ? wake-up from wake terminal figures 7 , 8 , and 9 on page 9 show device application circuit and detail of wake-up operations. wake-up from lin bus (awake transitional mode) a wake-up from the lin termina l switching from recessive to dominant state (switch from v sup to gnd) can occur. this is achieved by a node sending a wake-up frame on the bus. this condition internally wakes up the interface, which switches the inh terminal to a high level to enable the voltage regulator. the devic e switches into the awake mode. the microcontroller and the complete application power up. the microcontroller must switch the en terminal to a high level to allow the device to leave the awake mode and turn it into normal mode in order to allow communication on the bus. wake-up from internal node activity (normal mode) the application can internally wake up. in this case the microcontroller of the applicati on sets the en terminal in the high state. the device switches into normal mode. wake-up from wake terminal (awake transitional mode) the application can wake up with the activation of an external switch. refer to table 1, 8-soicn terminal definitions on page 3 . figure 10. operational and tr ansitional modes state diagram power-up/ sleep awake normal en low lin bus or wake terminal en high wake-up en high (local wake-up event) 1.0 to 20 kbps v pwr > 7.0 v note refer to table 5 for explanation. v pwr < 7.0 v v pwr < 7.0 v v pwr < 7.0 v down
analog integrated circuit device data freescale semiconductor 13 33399 functional device operation protection electrostatic discharge (esd) the 33399 has two human body model esd values. all terminals can handle 4.0 kv. the lin bus terminal, with respect to ground, can handle 5.0 kv. electromagnetic compatibility radiated emission on lin bus output line radiated emission level on the lin bus output line is internally limited and reduced by active slew rate control of the output bus driver. figure 11 shows the results in the frequency range 100 khz to 2.0 mhz. electromagnetic immunity (emi) on the lin bus terminal, the 33399 offers high emi level from external disturbance occurring at the lin bus terminal in order to guarantee communication during external disturbance. on the wake input terminal, an internal filter is implemented to reduce false wake-up during external disturbance. noise filtering noise filtering is used to protect the electronic module against illegal wake-up spikes on the bus. integrated receiver filters suppress any high-frequency (hf) noise induced into the bus wires. the cut-off frequency of these filters is a compromise between propagation delay and hf suppression. figure 11. radiated emission in normal mode table 5. explanation of operational and transitional modes state diagram operational/ transitional lin inh en txd rxd sleep mode recessive state, driver off. 20 a pullup current source. low low x high impedance. awake recessive state, driver off. high low x low. normal mode driver active. 30 k ? pullup active. high high low to drive lin bus in dominant. high to drive lin bus in recessive. report lin bus level: ? low lin bus dominant ? high lin bus recessive x = don?t care.
analog integrated circuit device data 14 freescale semiconductor 33399 typical applications typical applications the 33399 can be configured in several applications. figures 12 and 13 show slave and master node applications. an additional pullup resistor of 1.0 k ? in series with a diode must be added when the device is used in the master node. figure 12. slave node typical applicat ion with wake input switch and inh (switchable 5.0 v regulator) figure 13. master node typical device ap plication with mcu wake-up from stop mode (non-switchable 5.0 v regu lator, mcu stop mode) actuator sci mcu driver m 12v 5.0v inh 5.0 v lin bus v reg i/o v dd external switch rxd txd en lin vsup v ref logic gnd driver receiver bias inh protection wake-up wake 30 k ? 33399 v pwr regulator regulator control actuator sci mcu driver m 5.0 v lin bus master node pullup irq 5.0 v i/o v dd i/o(2) rxd txd en lin vsup v ref logic gnd driver receiver bias inh protection wake 30 k ? 1.0 k ? 33399 v pwr external switch 12v 5.0v regulator wake-up regulator control
analog integrated circuit device data freescale semiconductor 15 33399 package dimensions package dimensions important for the most current revision of the package, visit www.freescale.com and do a keyword search on the 98a drawing number below. style 4: pin 1. anode 2. anode 3. anode 4 anode style 1: pin 1. emitter 2. collector 3. collector 4 emitter style 2: pin 1. collector, die, #1 2. collector, #1 3. collector, #2 4 collector #2 style 3: pin 1. drain, die #1 2. drain, #1 3. drain, #2 4 drain #2 l h x 45? c seating plane s b m 0.25 a s c b a1 c a 0.10 1 4 5 8 m b m 0.25 d e h a b e dim min max millimeters a 1.35 1.75 a1 0.10 0.25 b 0.35 0.49 c 0.19 0.25 d 4.80 5.00 e 1.27 bsc e 3.80 4.00 h 5.80 6.20 h 0? 7? l 0.40 1.25 0.25 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions are in millimeter. 3. dimension d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. d suffix 8-terminal soic narrow body plastic package 98asb42564b issue t
MC33399 rev 5.0 02/2005 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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